This work introduces a novel mixed-dimensional reconfigurable field effect transistor (RFET) that combines a silicon nanowire (1D) with hexagonal boron nitride (hBN, 2D) as the gate dielectric. The RFET can dynamically switch between n- and p-FET by adjusting gate potentials. Using hBN for encapsulation improves electrical performance, reducing hysteresis by 10–20 V and increasing the on–off ratio by an order of magnitude (up to 10^8). Enhanced electrostatic top gate coupling improves subthreshold swing values, with significant gains in n- and p-conduction. This technology promises reduced device count, lower power consumption, and advancements in electronic circuitry.

This publication and dataset were published in ACS Applied Materials & Interfaces on 22nd August 2023.

Citation: Sayantan Ghosh, Muhammad Bilal Khan, Phanish Chava, Kenji Watanabe, Takashi Taniguchi, Slawomir Prucnal, René Hübner, Thomas Mikolajick, Artur Erbe, and Yordan M. Georgiev
ACS Applied Materials & Interfaces 2023 15 (34), 40709-40718
DOI: 10.1021/acsami.3c04808

The paper presents a compact model of a junctionless nanowire transistor (JLNT), based on J. P. Collinge’s model and implemented in Matlab, designed for real-time air-pollution sensors. The model’s accuracy is validated against experimental measurements of prototypes fabricated at the Helmholtz-Zentrum Dresden-Rossendorf using advanced lithography and etching processes. The modeled and fabricated devices, created on ultra-thin SOI substrates, show an average integral error between 2.83% and 9.30% when compared to measured electrical characteristics, demonstrating the model’s reliability for different device configurations.

This paper is a   conference proceedings from the 2023 46th International Spring Seminar on Electronics Technology (ISSE) that took place in Timisoara, Romania between 10-14 May 2023.

Citation: G. Angelov et al., “Compact Model of Junctionless Nanowire Transistor for Air-Pollution Sensor,” 2023 46th International Spring Seminar on Electronics Technology (ISSE), Timisoara, Romania, 2023, pp. 1-5, doi: 10.1109/ISSE57496.2023.10168462.

Si nanowires-based devices are used for various applications. The nanowires have a high surface-to-volume ratio which among other properties makes them suitable for sensing applications. The sensing devices for “RADICAL” are, therefore, being fabricated on a nanowires platform. The nanowires are fabricated using a top-down process. Electron beam lithography and dry etching processes are used details of which are given in the experimental section. Furthermore, this manuscript reports a reproducible silicidation process of these nanowires.

This publication and dataset were published in ACS Langmuir on 3rd Dec 2021.

Citation: Muhammad Bilal Khan, Slawomir Prucnal, Sayantan Ghosh, Dipjyoti Deb, René Hübner, Darius Pohl, Lars Rebohle, Thomas Mikolajick, Artur Erbe, and Yordan M. Georgiev. Langmuir 2021 37 (49), 14284-14291. DOI: 10.1021/acs.langmuir.1c01862

A 3D model of silicon three gate nanowire junctionless transistor is developed in COMSOL Multiphysics. It is based on Gummel approach with Green’s functions. The model describes output I-V characteristics. Modeling results are verified against reference experimental data with average accuracy of 11%. Simulation of gate materials with different work functions that are used in practice is performed. The charge distribution along the nanowire depending on gate length is also studied.

This paper is a   conference proceedings from the MIEL conference that took place in Niš, Serbia between 12-14 September 2021. 

Citation: R. Rusev et al., “COMSOL Model of a Three-Gate Junctionless Transistor,” 2021 IEEE 32nd International Conference on Microelectronics (MIEL), 2021, pp. 93-96, doi: 10.1109/MIEL52794.2021.9569053.

Channel length influence on the nanowire parameters and characteristics at different gate voltages for applications in junctionless transistors (JLTs) are analyzed. The density-gradient effective mass tensor of the charge carriers is studied. The results obtained are used to indicate a compromise between performance and minimum dimensions for JLT sensor applications.

This paper is a   conference proceedings from the Mixed Design of Integrated Circuits and Systems (MIXDES) conference that took place in Łódź, Poland between 24-26 June 2021. 

Citation: R. Rusev et al., “Study of Nanowire Characteristics of a Junctionless Transistor Depending on the Gate Length,” 2021 28th International Conference on Mixed Design of Integrated Circuits and System, 2021, pp. 184-187, doi: 10.23919/MIXDES52406.2021.9497541.